Hackaday

Spectre And Meltdown: How Cache Works

The year so far has been filled with news of Spectre and Meltdown. These exploits take advantage of features like speculative execution, and memory access timing. What they have in common is the fact ...
GitHub

vasusingh04/cache-simulator-cpp

A configurable CPU cache simulator implemented in C++ that models set-associative caches and analyzes cache performance using hit/miss statistics and Average Memory Access Time (AMAT). This project ...
Ars Technica

CPU Registers and associative caches 101

I have a certain basic understanding of how CPUs are made up with functional blocks, stages in a pipeline, why instructions are decoded and dispatched, and a naive understanding of cache hierarchy.
IEEE

TDV Cache: Organizing Off-Chip DRAM Cache of NVMM from a Fusion Perspective

Abstract: Emerging Non-Volatile Memory (NVM) provides both larger memory capacity and higher energy efficiency, but has much longer access latency than traditional DRAM, thus DRAM can be used as an ...
TechRepublic

Design of Cache Memory with Cache Controller Using VHDL

The authors report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds comparable with the operation of the ...